Low noise field effect transistor with channel having subsurface portion of high conductivity

ABSTRACT

A PN junction gated field effect transistor is described in which the channel region is provided with a subsurface portion of higher conductivity than the outer surface of such channel at an intermediate position between the outer surface and the bottom of the channel in order to reduce the noise caused by surface recombination of current carriers and other surface effects, to about one-tenth its previous noise level. This subsurface portion of high conductivity is preferably formed by providing an oxide layer which, during diffusion of the channel, gathers the doping impurity from the surface of the channel to reduce the conductivity of such surface. A further method is to diffuse compensating impurities into the channel which invert the channel surface to an intrinsic material while leaving a subsurface portion of high conductivity.

United States Patent ml Bresee et a1.

[ LOW NOISE FIELD EFFECT TRANSISTOR WITH CHANNEL HAVING SUBSURFACEPORTION OF HIGH CONDUCTIVITY [75] Inventors: Heber .l. Bresee. Campbell.Calif:

James L. Bowman. Portland. Oreg.

[73] Assignee: Telttronix. Inc.. Beaverton. Oreg.

[22] Filed: Dec. 19. I973 {21] Appl. No.: 426.259

Related US. Patent Documents Reissue of:

[64] Patent No.: 3.656.031

Issued: Apr. Il. 1972 Appl. No.: 97.730 Filed: Dec. 14. I970 [52] U.S.Cl. 357/22: 357/21; 357/58; 357/52; 357/91 [51] Int. Cl. H01! 5/00 [58]Field of Search..... 317/235 A, 235 T. 235 AD. 317/235 AG. 357/21. 22.13. 58.52.91

[56] References Cited UNI ED STATES PATENTS 3.268.374 8/1966 Anderson148/175 3.316.131 4/1967 Wisman..... 148/175 3.409.912 11/1968 Zuleeg rr 3I7/235 3.413.531 ll/1968 Lcith 317/235 3.414.782 l2/l968 Lin et a1.317/235 3.472.710 l0/1969 Welty i i [48/175 3.653.978 4/1972 Robinson eta1.. l48/l.5 3.7l7.5l6 2/1973 Hatchcr ct al. 148/187 [In E Re. 28.500

[ Reissued July 29. 1975 OTHER PUBLICATIONS W. George. "Optim. of theNeutron Rad. Tol. of Junction Field Effect Trans. IEEE Trans on Nuc.Sc.. Vol. NS-16. Dec. I969. pp. 8l-86 S. HSU. "Surface Related l/f Noisein MOS Transistors." Solid State Electronics. Vol, 13. 1970. pp.

Primary E.taniiner-Andrew J. James Assistant Bummer-Joseph E. Clawson.Jr Attorney. Agent. or Firm-Klarquist. Sparkman. Campbell. Leigh. Hall &Whinston l l ABSTRACT A PN junction gated field effect transistor isdescribed in which the channel region is provided with a subsurfaceportion of higher conductivity than the outer surface of such channel atan intermediate position between the outer surface and the bottom of thechannel in order to reduce the noise caused by surface recombination ofcurrent carriers and other surface effects. to about one-tenth itsprevious noise level. This suhsurface portion of high conductivity ispreferably formed by providing an oxide layer which. during diffusion ofthe channel. gathers the doping impurity from the surface of the channelto reduce the conductivity of such surface. A further method is todiffuse compensating impurities into the channel which invert thechannel surface to an intrinsic material while leaving a subsurfaceportion of high conductivity.

10 Claims. 5 Drawing Figures Reissued July 29, 1975 Re. 28,500

FIG. 3

l6 IO 22 22 22 P 40 N x P+ FIG. 4

I4 \fi&\\ FIG 5 l2" P |& 42 O '6 22 22 6 22 .\\\\\\\\w\\\\\\\\ l2' 46 44rZl 5 E |o" Q: 2 ,T0? GATE 8 10*" a? z 8.; \Asouacz AND DRAIN U o+ll E30 26 ,suBsuRFAcE PORTION g8 |OH7 P l g x 24CHIANNEL E [0H6 K E g IJBOTTOM GATE na l l FIG. 2

JAMES L.BOWMAN HERBER J. BRESEE INVENTORS.

BUCKHORN, BLORE, KLARQUIST & SPARKMAN ATTORNEYS LOW NOISE FIELD EFFECTTRANSISTOR WITH CHANNEL HAVING SUBSURFACE PORTION OF HIGH CONDUCTIVITYMatter enclosed in heavy brackets I: appears in the original patent butforms no part of this reissue specification; matter printed in italicsindicates the additions made by reissue.

BACKGROUND OF THE INVENTION The subject matter of the present inventionrelates generally to semiconductor electronic devices and, inparticular, to field effect transistors of the PN junction gated type.The channel region of the field effect transistor is provided with asubsurface portion of high conductivity in order to reduce noise in theoutput signal of such transistor by minimizing surface effects includingcurrent carrier recombination of electrons and holes. Since most of thechannel current flows through this subsurface portion, the surfacedefects do not cause as much recombination as with a conventional fieldeffect transistor.

The field effect transistor of the present invention is especiallysuitable for use in an integrated circuit such as that shown inco-pending US. Pat. application, Ser. No. 697,055 filed Jan. 11, I968,by H. .l. Bresee, one of the joint inventors of the present invention.As shown in this pending application, the diffused channel portion ofprevious field effect transistors is provided with a doping impurityconcentration having a maximum value at the surface of such channel andcontinu ously decreasing to a minimum value at the bottom of thechannel. This is the normal impurity concentration profile producedduring diffusion of impurities into semiconductor material.Unfortunately, such a diffused channel has the disadvantage that theregion of highest conductivity is at the surface of the channel so thatmuch of the channel current flows through surface defects which act asrecombination centers with the result that noise is produced in theoutput signal of the transistor due to recombination and other surfaceeffects. This problem is avoided by the subsurface portion of highconductivity used in the channel of the present field effect transistor.Thus, such subsurface portion has peak value of conductivity of, forexample, 9 X 10*" atoms per cubic centimeter, spaced below the surfaceof the channel, a distance of about 0.5 microns, and located at anintermediate position between the outer surface and the bottom of thechannel. The impurity concentration of the channel decreases from suchpeak value to an outer surface concentration of, for example, 3 X latoms per cubic centimeter. and to a bottom gate junction concentrationof, for example, 7 X atoms per cubic centimeter. As a result ofproviding this subsurface portion of highest conductivity, the noise inthe output signal of the transistor is reduced to a level of aboutone-tenth that of previous field effect transistor.

It is, therefore, one object of the present invention to provide animproved field effect semiconductor device having a low level of noisein its output signal.

Another object is to provide a field effect transistor with a channelregion having a subsurface portion of higher conductivity than its outersurface to reduce noise due to surface recombination of current carriersand other surface effects.

An additional object of the invention is to provide a PM junction gatedfield effect transistor having such a channel region formed by diffusionin which an oxide layer is provided on the outer surface of the channelto cause doping impurity to migrate from such surface into the oxidelayer which is later removed to leave the outer surface with a lowerimpurity concentration than a subsurface portion of the channel.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of thepresent invention will be apparent from the following detaileddescription of certain preferred embodiments thereof, and from theattached drawings of which:

FIG. I is a sectional view of one embodiment of the field effecttransistor of the present invention;

FIG. 2 is a diagram of the doping impurity concentration curves of thesemiconductor regions in the field effect transistor of FIG. I;

FIG. 3 is a sectional view of a second embodiment of the field effecttransistor of the present invention;

FIG. 4 is a sectional view of a third embodiment of the field effecttransistor of the present invention; and

FIG. 5 is a sectional view of a fourth embodiment of the field effecttransistor of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS As shown in FIG. I, oneembodiment of the field effect semiconductor device of the presentinvention is a PN junction gated field effect transistor formed on asubstrate member ll) of any suitable monocrystalline semiconductormaterial. The substrate member 10 may be made of N type siliconsemiconductor material having a uniform concentration of phosphorousdoping impurity. A channel region 12 of P-type silicon semiconductormaterial is formed by diffusing boron doping impurity into the substrateI0 to provide such channel with a subsurface portion of higherconductivity than its outer surface in a manner hereafter described. Asource region l4 and a drain region l6 of P+ type silicon semiconductormaterial are also formed by diffusing more boron doping impurity intothe channel region 12 at the opposite ends of such channel region. Thesource and drain form ohmic contacts with the channel. A top gate regionl8 of N type silicon semiconductor material is formed by diffusingphosphorous doping impurity into the channel 12 at an intermediateposition on the channel surface between the source and drain. The topgate region 18 forms a PN junction gate with the channel region whichcontrols the flow of channel current between the source and drain in aconventional manner. An insulating layer of silicon dioxide 20 isprovided over the outer surface of the channel portion 12 and the otherportion of the upper surface of the substrate 10. A plurality of metalcontacts 22 are provided through openings in the insulating layer 20into contact with the source 14, drain l6, top gate l8, and thesubstrate l0. The substrate acts as the back gate electrode for thechannel at the PN junction formed between such substrate and thechannel. It should be noted that the back gate region 10 may also beprovided by an epitaxial layer of uniform resistivity provided on asubstrate member forming part of an integrated surface as shown in theabove-mentioned copending U.S. Pat. application, Ser. No. 697,055 ofBresee.

The method of manufacture of the field effect transistor of FIG. I maybe similar to that shown in the above-mentioned patent application. Ser.No. 697,055. except for the formation of the channel region 12. As shownin FIG. 2, the channel region I2 has an impurity concentration curve 24with an outer surface value of about 3 X l" atoms per cubic centimeterand increases to a peak value 26 of about 9 X 10" atoms per cubiccentimeter at a subsurface portion spaced at a distance of about 0.5microns below the surface. The channel concentration curve 24 decreasesin value from the peak point 26 to its minimum value of about 7 X 10*atoms per cubic centimeter at the bottom of the channel approximately2.l microns from the surface. The bottom of the channel is determined bythe intersection of such channel curve with a horizontal line 28representing the uniform concentration of the back gate region 10 ofabout 7 X l0 atoms per cubic centimeter. Thus. the subsurface channelportion 26 of highest conductivity is located at an intermediateposition between the outer surface and the bottom of the channel. Normaldiffusion of the channel would provide a concentration curve 30, shownin dash lines. which has a surface concentration of about 2 X l0 atomsper cubic centimeter that is its portion of maximum conductivity. Curve30 decreases continuously in concentration from its surface value to itsportion of minimum conductivity at the bottom of the channel. However,in the present invention, some of the doping impurity is removed fromthe surface by migration from the channel surface into an oxide layercoated over such surface to leave the subsurface portion 26 of maximumconductivity. This migration is caused by heating the oxide coatedsemiconductor member I0 during the channel diffusion step. Thus, aboutfive minutes after the start of the channel diffusion drive cycle, wetoxygen containing water vapor is introduced into the system which causessilicon oxide layer to form on the surface of the channel early in thediffusion. This oxide layer getters" the boron doping impurity from thesurface of the channel and causes the surface value of the impurityconcentration curve to reduce from curve 30 to curve 24, as shown inFIG. 4. As a result, a subsurface portion of higher conductivity thanthe outer surface and having a peak value of 26 is formed in the channelspaced about 0.5 microns below the surface of such channel. This oxidelayer is subsequently removed before the source, drain, and top gateregions are diffused into the channel.

As shown in FIG. 2, the diffused source and drain regions l4 and 16having a concentration curve 32 which decreases from a surface value ofabout IO atoms per cubic centimeter to the point where it intercepts thechannel curve 24 at a value of approximately 6X10 atoms per cubiccentimeter about L25 microns from the surface of the channel at thebottom of the source and drain regions. Similarily, the top gate region18 has a concentration curve 34 formed by dif fusion which decreasesfrom a surface value of about 4 X 10* atoms per cubic centimeter to aminimum value of about 6 X l0 atoms per cubic centimeter where itcrosses the channel curve 24 so that the depth of the top gate region 18is also about 1.25 microns. It should be noted that all of the elementsof the field ef fect transistor except the back gate region II] areformed by diffusion and that the channel region has an impurityconcentration of lower surface value and lower average slope than any ofthe concentrations oi the other diffusions. This provides the channelwith a high resistance which is more uniform throughout its depth toenable the channel concentration to be more easily reproduced duringproduction as set forth in the above-mentioned co-pending application.

Another embodiment of the field effect transistor of the presentinvention is shown in FIG. 3 which is similar to that of FIG. I so thatthe same reference numerals have been used to designate like parts.However, the channel portion 12 of the field effect transistor of FIG. 3differs from that of FIG. I in that it is formed by an epitaxial outerlayer 36 of P type semiconductor material over a diffused layer 38 of Ptype semiconductor material. Thus, the epitaxial layer 36 of highresistance semiconductor material forms the outer surface of the channelregion 12 so that a subsurface channel portion of highest conductivityis provided by the diffused layer 38. This subsurface portion ispositioned at the junction between the bottom of the epitaxial layer 34and the top of the diffused layer 38 because such diffused layer has aconcentration curve similar to curve 30, in FIG. 2.

A third embodiment of the field effect transistor of the presentinvention is shown in FIG. 4. This embodiment is similar to that of FIG.3 except that the channel region 12 is provided with an I type intrinsicsemiconductor layer 40 over a P type diffused layer 42. The intrinsiclayer 40 is formed by diffusing N type impurities, such as phosphorous,into the surface of the P type diffused layer 42 until such N typeimpurities compensate for the P type impurities to form an intrinsicregion of high resistivity. As a result, a subsurface portion of highestconductivity is provided in the channel region 12" by the layer 42 at aposition adjacent the junction between the bottom of the intrinsicregion 40 and the top of the P type region 42.

FIG. 5 shows a fourth embodiment of the field effect transistor of thepresent invention which is similar to that of FIG. 1 except that thechannel region 12" is provided with an intermediate layer 44 of P+ typesemiconductor material within a diffused P- type layer 46. Theintermediate layer 44 is formed by ion implantation to provide asubsurface channel portion of highest conductivity. Thus, the implantedP+ type layer 44 is produced by bombarding the P type layer 46 with ionsof P type doping material which are accelerated to a high velocity sothat they penetrate into the layer 44 and stop at a point beneath thesurface of such layer.

It will be obvious to those having ordinary skill in the art that manychanges may be made in the abovedescribed details of the preferredembodiment of the present invention without departing from the spirit ofthe invention. Therefore, the scope of the present invention should onlybe determined by the following claims.

We claim:

1. In a field effect semiconductor device having a substrate of oneconductivity type including source and drain regions of the otherconductivity type and a channel portion of the other conductivity typeextending be tween the source and drain regions with a gate electrodedisposed thereon. the improvement comprising.

said channel portion having an outer surface on one side of saidsubstrate, a bouom portion. and a subsurface portion of higherelectrical conductivity relative to and spaced below said outer surfaceof said channel at an intermediate position between said outer surfaceand [the] said bottom portion of said channel for reducing the noise inthe output signal of said device, said subsurface portion having adoping impurity concentration which is several times greater than thatofsaid outer surface and said bottom portion of said channel, said outersurface, said bottom portion, and said subsurface portion being of thesame conductivity type 2. A semiconductor device in accordance withclaim 1 which is a PN junction gated field effect transistor having atleast one gate region of opposite type conductivity to said channelregion forming a PN junction gate with said channel region.

3. A field effect transistor in accordance with claim 2 in which thechannel region has a doping impurity concentration which increases froman intermediate value at the outer surface of the channel to a peakvalue in said subsurface portion of highest conductivity and decreasesfrom said peak value to a minimum value at the bottom of said channel.

4. A field effect transistor in accordance with claim 3 in which saidpeak value is at least 0.5 microns below the surface of said channel,

5. A field effect transistor in accordance with claim 3 in which thesurface impurity concentration of the channel is less than that of thesource, drain or top gate regions of the transistor.

6. A field effect transistor in accordance with claim 2 in which thechannel region contains a diffused doping impurity, a portion of whichhas been removed from the surface of said channel region to leave saidsubsurface portion of highest conductivity.

7. A field effect transistor in accordance with claim 5 in which thechannel doping impurity is boron.

8. A field effect transistor in accordance with claim 2 in which thechannel region includes an outer epitaxial layer of low conductivityover a diffused layer containing the subsurface portion of highestconductivity.

9. A field effect transistor in accordance with claim 2 in which thechannel region has an outer surface layer of compensated intrinsicsemiconductor material containing donor and acceptor doping impurities,over said subsurface portion.

10. A field effect transistor in accordance with claim 2 in which thesubsurface portion of highest conductivity is provided by ion implanteddoping impurities,

UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTIONPATENT NO. RE. 28,500

DATED July 29, 1975 Reissued INV ENTORG) Heber J. Bresee and James L.Bowman tt is certified that error appears in the above-identified patentand that said Letters Patent are hereby corrected as shown below:

Column 1, line 57, "l0" should be lO Column 2, line 47, after "drain"insert -regions--;

Column 3, line 53, "having" should be have.

Signed and Scaled this second Day of December197$ [SEAL] A nest:

RUTH C. MASON C. IAISIIALI. DANN Arresting Officer Commissioner 0fParents Ind Trademarks

1. In a field effect semiconductor device having a substrate of oneconductivity type including source and drain regions of the otherconductivity type and a channel portion of the other conductivity typeextending between the source and drain regions with a gate electrodedisposed thereon, the improvement comprising: said channel portionhaving an outer surface on one side of said substrate, a bottom portion,and a subsurface portion of higher electrical conductivity relative toand spaced below said outer surface of said channel at an intermediateposition between said outer surface and (the ) said bottom portion ofsaid channel for reducing the noise in the output signal of said device,said subsurface portion having a doping impurity concentration which isseveral times greater than that of said outer surface and said bottomportion of said channel, said outer surface, said bottom portion, andsaid subsurface portion being of the same conductivity type) .
 2. Asemiconductor device in accordance with claim 1 which is a PN junctiongated field effect transistor having at least one gate region ofopposite type conductivity to said channel region forming a PN junctiongate with said channel region.
 3. A field effect transistor inaccordance with claim 2 in which the channel region has a dopingimpurity concentration which increases from an intermediate value at theouter surface of the channel to a peak value in said subsurface portionof highest conductivity and decreases from said peak value to a minimumvalue at the bottom of said channel.
 4. A field effect transistor inaccordance with claim 3 in which said peak value is at least 0.5 micronsbelow the surface of said channel.
 5. A field effect transistor inaccordance with claim 3 in which the surface impurity concentration ofthe channel is less than that of the source, drain or top gate regionsof the transistor.
 6. A field effect transistor in accordance with claim2 in which the channel region contains a diffused doping impurity, aportion of which has been removed from the surface of said channelregion to leave said subsurface portion of highest conductivity.
 7. Afield effect transistor in accordance with claim 5 in which the channeldoping impurity is boron.
 8. A field effect transistor in accordancewith claim 2 in which the channel region includes an outer epitaxiallayer of low conductivity over a diffused layer containing thesubsurface portion of highest conductivity.
 9. A field effect transistorin accordance with claim 2 in which the channel region has an outersurface layer of compensated intrinsic semiconductor material containingdonor and acceptor doping impurities, over said subsurface portion. 10.A field effect transistor in accordance with claim 2 in which thesubsurface portion of highest conductivity is provided by ion implanteddoping impurities.